1. Field of the Invention
The invention relates to data processing systems and, more particularly, to a method and apparatus for reducing noise, spikes and power consumption accompanying the transmission of data between subsystems, such as processors and memories of a data processing system.
2. Background Art
In a computer system, data is transmitted as a multi-bit data word between units such as processors and memories, by means of bus driver circuits which are particularly designed to generate output signals of sufficient power to transmit the signals over transmission lines extending between the units. One known problem that has been evident in the art is that a switching driver induces a current spike on a ground or power rail. This current spike causes voltage oscillations in the ground and power rails which are inductive and resistive by nature. The operation of other circuits connected to these rails may thus be adversely impacted. The simultaneous switching, i.e., changing from one signal state to another signal state, of several drivers aggravates the noise problem. Such noise resulting from circuit switching is generally referred to as delta-I noise.
In large-scale integrated circuitry, the internal circuit power is reduced by improvements resulting from greater integration, but the power required to drive the to transmit data between integrated circuit chips is not reduced. Further, the power-requirement for the transmission of data is increased with increases in the size of the data words. One prior art approach to reducing data transmission problems is to reduce. data traffic between a processor and a memory by the use of cache memory within the processor unit. However, cache memories increase the chip die size and cost.
A given integrated circuit chip and packaging technology can only guarantee reliable circuit operation if power budgets and noise budgets are not exceeded. Such budgets limit the number of transmission line drivers which can be switched simultaneously, which may in turn, limit the number of bits in a data word or the number of processors which can be interconnected in a multi-processor system. One prior art solution for eliminating these power and noise bottlenecks is to skew the switching times of individual bit drivers of a data transmitting bus or to reduce the switching speed of the drivers. Such techniques, however, typically have an adverse impact on system performance and do not reduce the driver power.
Most current high speed integrated circuitry uses what is known as CMOS technology whereas, historically, computer circuits have used bipolar circuits. A number of techniques which were effective to reduce current demand in bipolar circuits are not applicable to CMOS circuits. One such technique is the use of out-of-phase busses to provide noise cancellation of current spikes (delta-I noise) in memory subsystems. Coding of control busses to balance or nearly balance the number of ones is another technique. Precharging a bus to half ones and half zeros state has also been used to delta-I noise in the bipolar environment. However, none of these previous techniques are applicable in the CMOS environment.